From Carl Ebeling:
There will be a slower-paced, low-octane version of this talk in my PMP class Tuesday night (Feb. 2, 6:30, EE045) that you are welcome to attend.
Title: “Logic Synthesis Demystified”
Speaker: Ramine Roane (Abound Logic)
Abstract:
This talk will be a quick tour through logic synthesis techniques from High Level and RTL synthesis, to Boolean optimization and mapping.
It will discuss RTL optimization techniques (which are similar to compiler optimizations), as well as the evolution of Boolean optimization methods from truth-tables to S.O.P. and Boolean Networks (used in SIS), to BDDs (used in VIS), to AND-Inverter-Graphs and the use of SAT solvers (used in ABC), using examples to illustrate the concepts.